1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having shift redundancy circuits.
2. Description of the Related Art
Semiconductor memory devices may have defective memory cell rows that can hinder the operation of the memory device and hence are undesirable. In the case where a defective memory cell row is present in a memory cell array, instead of controlling its corresponding word line, a word line control signal controls the respective next word line by being sequentially shifted in a direction, downward or upward. In conventional semiconductor memory devices, the word line selections are shifted in only one direction, upward or downward. Accordingly, in the case that a semiconductor memory device has two or more defective memory cell rows in a memory cell array, such semiconductor memory device may not be repairable. That is, conventional semiconductor memory devices are designed so that only one defective memory cell row can be repaired.
FIG. 1 is a schematic block diagram of a conventional semiconductor memory device. Referring to FIG. 1, a conventional semiconductor memory device includes a row decoder 10, a fuse circuit block 20, a shift redundancy circuit block 30, a fuse cut-out detecting circuit block 40, and a memory cell array 50.
The fuse circuit block 20 includes fuses f1 to fn which are serially connected. The semiconductor memory device shown in FIG. 1 has one spare memory cell row. Word lines R1 to Rn connected to memory cells are shifted through corresponding transmission gates T1a to Tna, T1b to Tnb. NMOS transistors Q1, Q2a to Qna, Q2b to Qnb connected to the corresponding word lines R1 to Rn are used to disable the corresponding word lines R1 to Rn having at least one defective memory cell. An output of the row decoder 10 is used as an input of a next memory cell row which is near the corresponding memory cell row in the downward direction as well as an input of the corresponding memory cell row.
Each fuse f1 to fn has an end connected to a power supply voltage Vcc and the other end connected to a ground voltage Vss. Since the fuses f1 to fn are connected between the power supply voltage Vcc and the ground voltage Vss, in the case that the memory cell array 50 does not have a defective memory cell row, the power supply voltage may be supplied to the shift redundancy circuit block 30. Accordingly, the transmission gates Tia (“i” is an integer) are turned on and the transmission gates Tib are turned off, so that the word lines R1 to Rn are connected to corresponding memory cell rows in the memory cell array 50. That is, the word lines R1 to Rn are not shifted. Further, the last transmission gate Tnb is turned off and the NMOS transistor Qn+1 connected to a spare word line Rn+1 is turned on, so that the spare word line Rn+1 is disabled.
On the other hand, in the case that the memory cell array 50 has a defective memory cell row, the fuse corresponding to the defective memory cell row is cut out and shift redundancy circuits in the shift redundancy circuit block 30 are divided into two groups, a group receiving power supply voltage Vcc and a group receiving ground voltage Vss.
The shift redundancy circuits in the group receiving power supply voltage Vcc act as normal shift redundancy circuits, so that the word lines are not shifted. However, for the shift redundancy circuits in the group receiving ground voltage Vss, since the fuses are connected to the ground voltage Vss, the transmission gate Tia is turned off and the transmission gate Tib is turned on, so that the word lines are shifted. That is, assuming that there is a defective memory cell row, a transmission gate corresponding to the defective memory cell row is turned off, and a word line corresponding to the defective memory cell row is disabled by NMOS transistors Qia, Qib, so that the word line is shifted down by one row. As a result, a spare memory cell row positioned at the lowermost portion of the memory cell array 50 is used.
However, the conventional semiconductor memory device as described above is disadvantageous in that repairing efficiency is low when the semiconductor memory device has two or more spare memory cell rows. That is, since the word lines in the conventional semiconductor memory device are shifted in only one direction, upward or downward, even if two spare memory cell rows are provided to the semiconductor memory device, two defective memory cell rows can not be repaired when the two defective rows are presented in the same memory cell array block. Further, the conventional semiconductor memory device as shown in FIG. 1 is disadvantageous in that there is a leakage current caused by fuse resistance, and further the semiconductor memory device may malfunction due to the voltage drop when the series of fuses is long and the resistance of each fuse is high.